The present invention relates in general to a method of forming an insulating zone around an active zone in a semiconductor substrate.
The FIGS. 1A, 1B and 1C are partial sectional views that diagrammatically illustrate, by way of example, a conventional method of forming an insulating zone that bounds an active zone on which a control gate of a MOS-type transistor is be formed.
As is shown in FIG. 1A, the method starts with the formation of a groove that bounds an active zone 2 in a semiconductor substrate 1. The operation for excavating the substrate 1 so as to define the active zone 2 is performed while protecting the non-excavated parts of the substrate 1 by means of an insulating mask 3. The mask 3 is formed by a double layer which consists of a thin lower layer 3-1 that is directly in contact with the substrate and is typically made of silicon oxide (SiO2); this thin layer is adjoined by a thick layer 3-2 of silicon nitride (Si3N4). The groove is filled with an insulating material, thus forming an insulating zone 4. The groove is filled in two steps: formation of a thermal oxide on the bottom and on the walls of the groove, followed by filling with silicon oxide. In order to carry out this filling operation, deposition takes place, followed by planing to the level of the upper surface of the mask 3.
During the subsequent steps, illustrated in FIG. 1B, the mask 3 is removed and several steps are executed notably for cleaning. One consequence of the removal of the mask is that the insulating zone 4 exhibits a protrusion that projects from the surface of the active zone 2, which protrusion has a substantially rectilinear and vertical profile. During the cleaning steps a depression 5 could be formed at the base of the protrusion at the periphery of the active zone 2.
The surface of the active zone is subsequently covered with a thin insulating layer 6. At this stage generally sequences of steps for doping the active zone 2 by implantation/diffusion are generally carried out. Such operations are ignored herein, because they have no bearing whatsoever on the problems to be described hereinafter. The layer 6 is intended, for example to form the gate insulator of a MOS transistor. After the formation of this gate insulator 6, a layer 7 of a conductive material, generally being polycrystalline silicon, is deposited. In order to define a gate having a transistor-type structure, in the example illustrated herein a thick layer 8 of an anti-reflective coating material is deposited (this layer is generally referred to by the acronym Barc (Bottom Anti-Reflective Coating)), followed by the deposition of a mask of resin that defines the pattern of the gate to be formed (another procedure would be to deposit the resin mask first and then the anti-reflective material). The resin layer is not shown in FIG. 1B, because it is assumed that the sectional view is taken in a region of the active zone 2 where the gate does not extend. It is known to use typically a layer 8 of an organic type that enables suitable planing of the structure and that can also be readily removed. However, the etching selectivity for the layer 8 with respect to the superposed resin is low.
During the subsequent steps (illustrated in FIG. 1C), the conventional etching steps are performed so as to remove the layer 7 beyond the gate regions and other regions where conductive structures are to be formed.
A drawback of this type of method resides in the fact that, as is shown in FIG. 1C, after the steps for removing the layer 7 the structure is often polluted by residues of this layer. More specifically, residue 7-1 is liable to be left behind on the insulator 6, approximately at the center of the active zone 7, as well as residue 7-2 along the protrusion of the insulating zone 4.
As is shown in the diagrammatic partial plan view of FIG. 2, when forming continuous tracks the residues 7-1 and 7-2 cause short circuiting of conductive structures formed on the active zone 2 bounded by the insulating zone 4. For example, the conductive residues 7-1, 7-2 will cause the short circuiting of three conductive lines L1, L2 and L3 that traverse the active zone 2 and are insulated therefrom by an insulating layer.
In the case of control gates of transistors such short circuiting causes malfunctioning of the device in which they are included. Therefore, in the case of memory matrices of the dynamic random access type (DRAM) such switching may cause involuntary storage or erasure of data.
Therefore, it is an object of the present invention to propose a novel method of manufacture which enables elimination of the formation of parasitic residues during the etching of the conductive gate layer.
In order to achieve this object, the present invention provides a method of forming an insulating zone around an active zone in a semiconductor substrate, which method includes the following steps:
forming a groove around an active zone in said substrate;
filling the groove with a first material so as to form around the active zone, an insulating zone which projects from the surface of the substrate and forms a vertical protrusion at its periphery, and
blunting the angle of the protrusion of the insulating zone at the periphery of the active zone.
In one version of the method in accordance with the present invention the step a) for forming the groove is carried out by means of a mask that consists of at least a second material.
In a further version of the method in accordance with the present invention the step c) for blunting said angle includes the following steps:
etching said mask in such a manner that only a reduced thickness remains, and
carrying out a bombardment by means of particles.
In a further version of the method in accordance with the present invention the step c) for blunting said angle consists in performing simultaneous etching of the first and the second material, which etching has a selectivity ratio greater than one between the second and the first material.
According to a further version of the method in accordance with the present invention the step c) for blunting said angle consists of the sequential etching of small thicknesses of the first and the second material in order to eliminate the second material completely and to impart to said protrusion an angle of the order of 135 degrees relative to the surface of the substrate.
In another version of the method in accordance with the present invention the first material is silicon oxide (SiO2) and the second material is silicon nitride (Si3N4).
In a further version of the method in accordance with the present invention the particles are argon atoms.
In a further version of the method in accordance with the present invention said etching is performed by means of a mixture of hydrofluoric acid (HF) and ethylene glycol (CH2OHxe2x80x94CH2OH).
In another version of the method in accordance with the present invention a solution of hydrofluoric acid (HF) and a solution of phosphorous acid (H3PO4) are used in succession for etching the first material and for etching the second material, respectively.